1. Field of the Invention
The present invention relates to a technique for stabilizing a power supply.
2. Description of the Related Art
In a case of testing a semiconductor integrated circuit (which will be referred to as the “DUT” hereafter) such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, or the like, that makes use of CMOS (Complementary Metal Oxide Semiconductor) technology, electric current flows through flop-flops and latches in the DUT in the operating state in which a clock is supplied. When the clock supply is stopped, the circuit enters a static state, thereby reducing the current. That is to say, the sum total of consumed current (load current) that flows through the DUT changes over time according to the proportion (operating ratio) of gates (transistors) that are in the operating state, i.e., changes over time according to the test content.
A power supply circuit configured to supply a power supply voltage to the DUT is configured employing a regulator. Ideally, such a power supply circuit is capable of providing a constant power supply voltage regardless of the load current. However, in practice, such a power supply circuit has an output impedance that is not negligible. Furthermore, the impedance component between the power supply circuit and the DUT is also not negligible. Accordingly, such an arrangement has a problem of fluctuation in the power supply voltage due to fluctuation in the load.
Such fluctuation in the power supply voltage has a serious effect on the test margin to be applied to the DUT. Furthermore, such fluctuation in the power supply voltage also has an effect on the operation of other circuit blocks in the test apparatus, such as a pattern generator configured to generate a pattern to be supplied to the DUT, and a timing generator configured to control the transition timing of the pattern. This leads to deterioration of the precision of the test.
In order to solve such a problem, a technique has been proposed in which the power supply voltage is corrected according to a test pattern supplied to the DUT so as to stabilize the power supply voltage at the DUT terminal (Patent document 1).
[Patent Document 1]
    Japanese Patent Application Laid Open No. 2007-205813
In the technique disclosed in Patent document 1, such an arrangement compensates for the power supply voltage after it reads out a test pattern applied to the DUT. Accordingly, in some cases, such an arrangement cannot follow a rapid change in the power supply voltage, leading to a delay in the power supply voltage compensation according to the test pattern. Furthermore, such a compensation circuit is configured as a part of the power supply circuit. Accordingly, such an arrangement has a problem in that such a compensation circuit can compensate for the power supply voltage only in the frequency range limited by the impedance between the power supply circuit and the DUT. Moreover, such an arrangement requires a multi-bit D/A converter according to the range and resolution of the power supply voltage compensation.